This invention relates to digital logic devices implemented using CMOS integrated circuits.
Complex logical functions are commonly performed using chains of integrated circuit logic gates.
Static CMOS (complementary metal oxide semiconductor) logic gates employ a combination of one or more a p-type metal oxide semiconductor (PMOS) devices interconnected with one or more n-type metal oxide semiconductor (NMOS) devices to implement a desired logic function. The junction of the PMOS and NMOS transistors forms the output node for the gate.
Dynamic CMOS logic circuitry typically consists of a cascaded chain of logic stages, each consisting of NMOS logic connected to an output node which is precharged by one or more PMOS devices which are switched ON by an input clock signal. When the clock signal is inactive, the output node is selectively discharged by the NMOS devices which are controlled by the input signal values. In this arrangement, input signals applied to the first stage of the chain trigger the operation of the remaining stages in sequence, yielding a signal propagation effect akin to a line of falling dominos, and dynamic logic circuits are hence also called xe2x80x9cdomino logicxe2x80x9d circuits.
Domino logic increase the speed at which the information bearing signals can propagate through the circuit by precharging the gates during the first clock phase and evaluating the inputs during the second clock phase. However, domino logic consumes more power than static logic because the domino output precharges during every precharge phase and discharges during every evaluation phase in which the inputs evaluate to a discharged state.
Examples of CMOS domino logic circuits are described in U.S. Pat. Nos. 4,700,086, 5,369,621; 5,821,775; 6,275,071. Arrangements for increasing the speed of domino logic circuits are disclosed in U.S. Pat. Nos. 5,121,003; 5,208,490; 5,343,090; 5,661,675 and 5,796,282. Methods and apparatus for reducing the power consumption of domino logic circuits are disclosed in U.S. Pat. Nos. 5,880,968; 5,880,986; and 6,005,417.
A second family of devices called xe2x80x9cskewed logic gatesxe2x80x9d may also be used to increase the speed of signal propagation through a chain of gates. Skewed circuits are CMOS devices in which the sizes of the PMOS and NMOS transistors are adjusted to enable one of the transitions to be faster than the other. By changing the altering the drive characteristic of the PMOS and NMOS networks, performance comparable to dynamic circuits may be achieved while at the same time reducing clock power consumption. As described in U.S. Pat. No. 6,154,045, by alternately skewing gates in a chain of gates for fast rise and fast fall, the total signal delay through the chain of gates is reduced as compared to the delay experienced by a signal transmitted through a chain of similar gates that are not skewed (i.e. xe2x80x9cbalancedxe2x80x9d gates that have the sizes of the p-type and n-type gates ratioed for substantially equal rise and fall times).
The embodiment of the invention described below takes the form of a chain of logic gates comprising a first pulsed domino logic stage followed by a series of skewed static gates. The domino logic first stage receives a clocking pulse that preconditions the input for evaluation only during a brief window of time determined by an input pulse. The pulsed domino logic gate is followed by a sequence of skewed static gates which provide the speed of domino circuits at reduced power.
The use of a single stage pulsed domino circuit reduces power consumption by replacing all but the first stage of the domino logic chain with skewed logic gates and by substituting a pulsed domino stage for the conventional clocked domino circuit. This arrangement significantly reduces the load on the clock, provides better tolerance to cross-coupling and noise, and proves better Vcc/Vt scaling than conventional domino logic chains.
These and other features and advantages may be better understood by considering the following detailed description of a preferred embodiment of the invention. In the course of this description, frequent reference will be made the attached drawings.